IVERILOG = iverilog
SIMULATOR = vvp

RTL_SOURCES = rtl/fpu_add.v \
              rtl/fpu_div.v \
              rtl/fpu_double.v \
              rtl/fpu_exceptions.v \
              rtl/fpu_mul.v \
              rtl/fpu_round.v \
              rtl/fpu_sub.v

TB_SOURCES = tb/fpu_TB.v

INCLUDES = -Irtl -Itb

ALL_SOURCES = $(RTL_SOURCES) $(TB_SOURCES)

OUTPUT = tb.out

TB_TOP_MODULE = fpu_tb

.PHONY: verify synthesis verify_netlist clean help

verify:
	$(IVERILOG) $(ALL_SOURCES) $(INCLUDES) -s $(TB_TOP_MODULE) -o $(OUTPUT) && ./$(OUTPUT)

synthesis:
	python synthesis.py

verify_netlist:
	for file in syn/nangate45/*; do \
		$(IVERILOG) $$file $(TB_SOURCES) $(LIB_DIR)/nangate45/verilog/nangate45.v $(INCLUDES) -s $(TB_TOP_MODULE) -o $(OUTPUT) && ./$(OUTPUT); \
	done
	

clean:
	rm -rf $(OUTPUT) ./rpt ./scripts ./syn

help:
	@echo "Available targets:"
	@echo "  make verify     - Compile and run the testbench"
	@echo "  make synthesis  - Run synthesis"
	@echo "  make clean      - Remove generated files"
	@echo "  make help       - Show this help message"
